A fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic

A new design methodology for mapping circuits is discussed in this paper. It proposes two new techniques for mapping circuits. The rst method, known as the odd-level transistor replacement (OTR) method, has a goal that is similar to that of technology mapping, but without the restriction of a xed library size. The second technique, the Static/PTL method, uses a mix of static CMOS and pass transistor logic (PTL) to realize the circuit, using the relation between PTL and binary decision diagrams. The methods are very efcient and can handle all of the ISCAS85 benchmark circuits in minutes. A comparison of the results with traditional technology mapping using SIS on di erent libraries shows an average delay reduction about 40% for OTR, and an average delay reduction above 50% for the Static/PTL method.